The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as P-channel MOS (PMOS), N-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in a MOS transistor, an active device generally includes a source and drain region and a gate electrode that modulates current between the source and drain regions.
One important step in the manufacturing of such devices is the formation of devices, or portions thereof, using photolithography and etching processes. In photolithography, a wafer substrate is coated with a light-sensitive material called photo-resist. Next, the wafer is exposed to light; the light striking the wafer is passed through a mask plate. This mask plate defines the desired features printed on the substrate. After exposure, the resist-coated wafer substrate is developed. The desired features as defined on the mask are retained on the photoresist-coated substrate. Unexposed areas of resist are washed away. The wafer, with the desired defined features, is etched. Depending upon the production process, the etching may either be a wet etch in which liquid chemicals are used to remove wafer material or a dry etch in which wafer material is subjected to a radio frequency (RF) induced plasma. A challenge in the etching process is maintaining control over the etching of the features, notably in the source/drain electrode regions of the MOS transistor. A further challenge is to control the electrical characteristics of the source/drain region by establishing a suitable doping profile that provides good conductivity within the constraints of design rules which trend further into the sub-micron range.
Doping the source/drain regions of a MOS transistor is typically accomplished through ion implantation. Unmasked areas of the MOS transistor are subjected to a beam of dopant atoms. Ion implantation has a number of advantages, including the ability to precisely control the number of implanted dopant atoms into substrates, for example, within .+-.3% in a range of 1.times.10.sup.14 to 1.times.10.sup.18 atoms/cm.sup.3.
A significant disadvantage to ion implantation is that it causes damage to the material structure of the target. In the single-crystal substrate of the source/drain region crystal defects and even amorphous layers are formed. To restore the target material to its preimplantation condition, thermal processing (e.g., annealing) after implantation must be performed. In some cases, significant implantation damage can not be removed. Damage at the source/drain region can lead to high leakage currents or TED Transient Enhanced Diffusion) of dopants in the sub-micron realm where shallow source/drain regions are necessary.
Also the lateral distribution of implanted species (although smaller than lateral diffusion effects) is not zero. This is a limiting factor in fabricating some minimum sized device structures, such as the electrical channel length between source and drain in self-aligned MOS transistors.
In an effort to address the implant damage, in an example process, regions of epitaxial silicon are selectively grown over the source and drain regions of the MOS transistor after a first source/drain implant to build lightly doped drain (LDD) structures. Depending upon the polarity of the transistor, the source/drain implants will either be P-type for a PMOS transistor or N-type for an N-MOS transistor. These epitaxial regions are implanted with N+ or P+ species. The epitaxial regions are implanted with sufficient energy and dose to achieve continuity with the LDD implant in the substrate. The dopant atoms will diffuse into the silicon in essentially the same shape as the epitaxial regions to form the N+ or P+ source/drain junctions within at least a portion of the regions.
Typically, the more heavily doped source/drain regions have a deeper junction that the LDD regions. LDD regions may typically form to a depth of approximately 1000 angstroms. In NMOS devices, the doses required for this depth would normally be approximately 1-4.times.10.sup.13 atoms/cm.sup.2 of phosphorus or arsenic. With a source/drain diffusion, the second more heavily doped source and drain regions junctions are formed to a depth of approximately 1500 Angstroms below the silicon surface. In NMOS devices, the implant is typically arsenic at a dose of 5.times.10.sup.15 atoms/cm.sup.2. The depth of the source drain regions can be made deeper than the LDD regions.
A significant disadvantage of selective epitaxial growth is that localized epitaxial growth may occur along the sides of the epitaxial region that is the target area of the source/drain region. In addition, there may be some lateral formation of the epitaxial regions over the field oxide or sidewall oxide spacers. Any lateral growth is at least partially the result of the upward growth of the epitaxy over the silicon substrate. Selective epitaxial growth may work on a small scale. However, it is not likely a manufacturable process that could be integrated into a modern CMOS production line.
Sub-micron technologies require the formation of ultra shallow junctions for the source/drain extensions in order to minimize the short channel effects. The contact region however, will have to be deeper than the source/drain extensions to allow for the use of salicide technology. Salicide (Self-Aligned Silicide) technology involves depositing a metal over exposed silicon in a MOS structure. The deposited metal is reacted with the Si to form a silicide, usually in the source/drain regions as well as exposed poly-Si areas of the gate. Salicide technology is necessary to lower the extrinsic series resistance, reduce contact resistance, and minimize gate RC delays. To reduce Rs, silicide must be of a certain thickness, the thinner the silicide, the higher the resistance. Thicker silicide however, requires deeper source/drain junctions to reduce junction leakage. The deeper source/drain junctions can in turn lead to a degradation of short-channel effects (such as drain induced barrier lowering--DIBL) because of the additional charge sharing by the deep source/drain. These requirements represent conflicting demands for sub-micron (0.18 .mu.m) technologies. Efforts to circumvent this limitation to the scaling of source/drain junctions are problematic.
Accordingly, there is a need for a semiconductor device having a source/drain structure that addresses these above-mentioned issues, is substantially free of defects, has predictable dimensions, and does not add extra manufacturing costs as the process technology is approaching fractional microns in feature sizes.